With the continuous development of science and technology, more and more electronic devices are widely used in people's daily life and work and bring great convenience to people's daily life and work, and these electronic devices become indispensable important tools to people currently.
Electronic devices tend to be miniaturized and portable. One main factor that determines miniaturization and portability of an electronic device is a packaging design of a chip in the electronic device. In a conventional chip packaging method, packaging is usually performed by using wire bonding. However, with the rapid development of integrated circuits, a size of a product cannot meet a desired requirement due to a long wire, therefore, a wafer level package (WLP) gradually becomes a more common packaging method instead of the wire bonding package. Wafer level packaging technology is a technology in which a whole wafer is packaged and tested and then the wafer is cut into independent chips, and a size of a packaged chip is exactly the same as that of a die. The wafer level package has the following advantages: multiple wafers can be processed at the same time, thereby leading to a high packaging efficiency; the whole wafer is tested before the wafer is cut, thereby simplifying a test process during packaging and reducing a test cost; and a packaged chip has advantages of being light, small, short and thin.
In the conventional wafer level packaging method, in order to protect a surface of a chip from being damaged and contaminated during a process of packaging the chip, a protection substrate is usually formed on a surface of the wafer to protect the wafer. After the chip is packaged, the protection substrate is to be peeled off, and the packaged wafer is cut finally to obtain multiple single-chip packages.
However, in the conventional technology, since the protection substrate is peeled off from the wafer in advance, the surface of the chip may still be damaged and contaminated during a cutting process or other processes subsequently, and strength of the chip package is weak.